[1]
[2]
[3]
[4]
[5]
[6]
Fig. 7. Improved DHNN system.
[7]
𝑉𝑏 are the total bias current and the dc supply voltage (Vb of 2.5
mV is used in our cell library [16, 17]), respectively. Dynamic
power dissipation at the frequency of 50 GHz and static power
dissipation of the whole designed circuit is 11.2 W and 1.46
mW, respectively.
According to the digital simulation results, computation time
of the whole system for two storage patterns with 8 pixels is
746.1 ps. The time to calculate the hi per storage pattern is 238.0
ps and the time to calculate each pixel is 29.8 ps. Computation
time of the whole system is proportional to the number of pixels
and storage patterns.
The designed DHNN circuit could not operate ℎ𝑖 in parallel,
because the ℎ𝑖 values are calculated by the PEs sequentially. To
resolve this, the bit count circuit used a trigger flip-flop (TFF)
cell (T1 cell) that can accumulate the binary stream of information and read and store the state. The result of the accumulation is passed to the register and the next PE; as a result, ℎ𝑖 is
calculated in parallel, as illustrated in Fig. 7. The new architecture reduces latency by a factor of number of storage pattern
over the original architecture.
IV. CONCLUSION
We investigated the hardware architecture for the SFQ
DHNN system that realizes designing the circuit with a small
footprint. We added registers to PE to parallelize the algorithm.
Digital circuit simulations indicates that the retrieve pattern is
converged to the storage pattern. This means the designed SFQ
DHNN system can be applied to image recognition. We designed the DHNN circuit with two storage patterns and eight elements. The circuit area was 6.5 mm × 2.3 mm and the circuit
was numerically simulated at up to 50 GHz clock frequencies,
assuming the use of the AIST-ADP2.
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