論文の公開元へReduction of interface and oxide traps in SiO₂/GaN MOS structures by oxygen and forming gas annealing
概要
Title
Reduction of interface and oxide traps in
SiO₂/GaN MOS structures by oxygen and forming
gas annealing
Author(s)
Mikake, Bunichiro; Kobayashi, Takuma; Mizobata,
Hidetoshi et al.
Citation
Applied Physics Express. 2023, 16(3), p. 031004
Version Type AM
URL
rights
https://hdl.handle.net/11094/90756
This Accepted Manuscript is available for reuse
under a Creative Commons AttributionNonCommercial-NoDerivatives 4.0 International
License after the 12 month embargo period
provided that all the terms of the licence are
adhered to.
Note
Osaka University Knowledge Archive : OUKA
https://ir.library.osaka-u.ac.jp/
Osaka University
Applied Physics Express
ACCEPTED MANUSCRIPT
Reduction of interface and oxide traps in SiO2/GaN MOS structures by
oxygen and forming gas annealing
To cite this article before publication: Bunichiro Mikake et al 2023 Appl. Phys. Express in press https://doi.org/10.35848/1882-0786/acc1bd
Manuscript version: Accepted Manuscript
Accepted Manuscript is “the version of the article accepted for publication including all changes made as a result of the peer review process,
and which may also include the addition to the article by IOP Publishing of a header, an article ID, a cover sheet and/or an ‘Accepted
Manuscript’ watermark, but excluding any other editing, typesetting or other changes made by IOP Publishing and/or its licensors”
This Accepted Manuscript is © 2023 The Japan Society of Applied Physics.
During the embargo period (the 12 month period from the publication of the Version of Record of this article), the Accepted Manuscript is fully
protected by copyright and cannot be reused or reposted elsewhere.
As the Version of Record of this article is going to be / has been published on a subscription basis, this Accepted Manuscript is available for reuse
under a CC BY-NC-ND 3.0 licence after the 12 month embargo period.
After the embargo period, everyone is permitted to use copy and redistribute this article for non-commercial purposes only, provided that they
adhere to all the terms of the licence https://creativecommons.org/licences/by-nc-nd/3.0
Although reasonable endeavours have been taken to obtain all necessary permissions from third parties to include their copyrighted content
within this article, their full citation and copyright line may not be present in this Accepted Manuscript version. Before using any content from this
article, please refer to the Version of Record on IOPscience once published for full citation and copyright details, as permissions will likely be
required. All third party content is fully copyright protected, unless specifically stated otherwise in the figure caption in the Version of Record.
View the article online for updates and enhancements.
This content was downloaded from IP address 133.1.116.47 on 07/03/2023 at 00:11
Page 1 of 13
cri
pt
Reduction of interface and oxide traps in SiO2/GaN MOS structures by
oxygen and forming gas annealing
Bunichiro Mikake, Takuma Kobayashi*, Hidetoshi Mizobata, Mikito Nozaki, Takayoshi Shimura,
and Heiji Watanabe
Graduate School of Engineering, Osaka University, Suita, Osaka 565-0871, Japan
*
us
E-mail: kobayashi@prec.eng.osaka-u.ac.jp
The effect of post-deposition annealing on the electrical characteristics of SiO2/GaN MOS devices
was investigated. While the key to the improvement was using oxygen annealing to form an
an
interfacial GaOx layer and forming gas annealing to passivate the remaining defects, caution must
be taken not to produce fixed charge through reduction of the GaOx layer. By growing the GaOx
layer with oxygen annealing at 800°C and performing forming gas annealing at a low temperature
of 200°C, it became possible to suppress the reduction of GaOx and to reduce the interface traps,
ce
pte
dM
oxide traps, and fixed charge simultaneously.
Ac
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
AUTHOR SUBMITTED MANUSCRIPT - APEX-107073.R1
1
AUTHOR SUBMITTED MANUSCRIPT - APEX-107073.R1
Gallium nitride (GaN) is suited for high-power and high-frequency device applications owing to
its superior material properties, such as wide band gap and high breakdown electric field.1–3)
cri
pt
AlGaN/GaN high electron mobility transistors (HEMTs) which rely on two-dimensional electron
gases (2DEGs) at the AlGaN/GaN interface have been developed for high-frequency
applications.2,4,5) In addition to Schottky-gate HEMTs,4–6) metal-insulator-semiconductor (MIS)gate HEMTs are a promising means to reduce the gate leakage.6–9) However, HEMTs are usually
normally-on because 2DEGs automatically form at the AlGaN/GaN interface due to piezoelectric
and spontaneous polarization.
From this perspective, vertical GaN metal-oxide-semiconductor field effect transistors
us
(MOSFETs) are appealing as they may achieve normally-off operation and also operate at high
voltages.10–13) Various dielectrics such as silicon dioxide (SiO2),14,15) aluminum oxide (Al2O3),16,17)
and aluminum silicate (AlSiO),18,19) have been investigated for GaN MOS devices. Among them,
SiO2 is extremely thermally stable and has a wide bandgap of about 9 eV. Thus, sufficiently large
an
conduction and valence band offsets form at the SiO2/GaN interface, which will prevent gate
leakage.
To achieve highly reliable and high-performance MOSFETs, optimization of the MOS
dM
structure is necessary. It has been reported that the formation of gallium oxide (GaOx) at the
SiO2/GaN interface is the key to reducing the interface traps.20–25) During plasma-enhanced
chemical vapor deposition (PECVD) of SiO2 on GaN, a thin GaOx layer is produced at the
interface due to oxidation of the GaN surface by the plasma.22,24) With post-deposition annealing
in an oxygen ambient (O2-PDA), the GaOx layer grows further, which reduces the interface state
density of the SiO2/GaN MOS structure to 1010 cm-2eV-1.22,24)
However, there is a drawback to GaOx formation in terms of threshold voltage (VTH) instability.
pte
When forming gas annealing (FGA; hydrogen (H2) annealing) is performed on a SiO2/GaN MOS
structure with a GaOx layer, the flat band voltage (VFB) shifts toward negative values.26,27) This is
most likely due to generation of positively charged oxygen vacancies through reduction of the
GaOx layer.26–31) By performing O2-PDA and FGA under appropriate temperature conditions, it is
possible to reduce the interface traps while suppressing the fixed charge generation.27)
ce
Nevertheless, it is unclear whether this strategy can minimize oxide traps as well. Minimization
of oxide traps is needed in order to suppress unwanted VTH drift during operation of MOS devices
and guarantee long-term reliability.
Therefore, in this study, we further investigated the effect of O2-PDA and FGA on the interface
properties and reliability of GaN MOS devices. We fabricated MOS structures under various
Ac
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Page 2 of 13
annealing conditions to control the oxidation and reduction reactions occurring at the SiO2/GaN
2
Page 3 of 13
interface. Interface properties and reliability were characterized through capacitance-voltage (CV) measurements and bias stress tests (or charge injection stress tests), respectively. Our aim was
cri
pt
to minimize the interface traps, fixed charge, and oxide traps simultaneously towards the goal of
fabricating highly reliable and high-performance GaN MOS devices.
MOS devices were fabricated on freestanding GaN (0001) substrates with n-type GaN
epilayers ([Si]: 2 × 1016 cm-3). The samples were first cleaned with acetone and 50%-hydrofluoric
(HF) acid. After that, SiO2 was deposited on the GaN by PECVD using a gas mixture of tetraethyl
orthosilicate (TEOS) and O2. In the initial deposition stage, a nitrogen-incorporated SiO2 layer of
about 5-nm thick was formed by introducing nitrogen (N2) gas into the chamber; this layer
us
prevents Ga from diffusing into the SiO2 dielectric.24) Then, a normal SiO2 layer about 80-nm
thick was deposited (total oxide thickness: 85 nm). After the deposition, O2-PDA was performed
at 600–800°C for 30 min, followed by FGA (3% H2/N2) at 200–500°C for 30 min. Table 1
describes the annealing conditions of samples prepared in this study. An as-deposited sample
an
without any annealing treatment was also prepared for comparison. For these SiO2/GaN samples,
MOS capacitors with Ni gate electrodes (100 μm in diameter) and Al back contacts were
fabricated for electrical characterization.
Figure 1(a) shows the bidirectional C-V characteristics of the fabricated SiO2/GaN MOS
dM
capacitors. For the as-deposited sample (as-depo.), a positive VFB shift with respect to its ideal
position (dashed line) and clockwise hysteresis were observed in the C-V characteristics. This
shift was due to the large number of electron traps at the interface. After O2-PDA at 800°C (O2800),
a decrease in the VFB shift as well as hysteresis occurred that was due to the GaOx growth at the
interface.22,24) However, a significant negative VFB shift was observed when additional FGA was
carried out at 500°C (O2800-H2500). This was likely caused by the reduction of the GaOx layer,
pte
which would have formed positive fixed charge related to oxygen vacancies.26–31) Figure 1(b)
describes the impact of O2-PDA and FGA. While the growth of the GaOx layer by O2-PDA is
helpful in passivating the interface traps, the layer will produce positive fixed charge when it is
subjected to FGA. There are two ways to deal with this situation. The first way is to lower the O2PDA temperature to suppress the growth of the GaOx layer (H2500, O2600-H2500). As shown in
ce
Fig. 1(a), a mostly ideal VFB position was indeed obtained for H2500 and O2600-H2500. ...
この論文で使われている画像
