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Published Papers
Journal Papers (related to Thesis)
1.
S. Kawai, T. Ueno, H. Ishikuro and K. Onizuka, "An Active Slew Rate Control Gate
Driver IC With Robust Discrete-Time Feedback Technique for 600-V Superjunction
MOSFETs," in IEEE J. Solid-State Circuits, vol. 58, no. 2, pp. 428-438, Feb. 2023.
2.
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for Drive Pattern Selection and Functional Safety Targeting Dependable SiC Application,"
in IEEE Trans. on Power Electron., vol. 38, no. 6, pp. 7079-7091, Jun. 2023.
Presentations at International Conference (related to Thesis)
1.
S. Kawai, T. Ueno, and K. Onizuka “A 4.5V/ns Active Slew-Rate-Controlling Gate Driver
with Robust Discrete-Time Feedback Technique for 600V Superjunction MOSFETs” IEEE
International Solid-State Circuit Conference, pp. 252-253, 2019.
2.
S. Kawai, T. Ueno, H. Ishihara, S. Takaya, K. Miyazaki, and K. Onizuka “A
1ns-Resolution Load Adaptive Digital Gate Driver IC with Integrated 500ksps ADC for
Drive Pattern Selection and Functional Safety Targeting Dependable SiC Application”
IEEE Energy Conversion Congress & Exposition (ECCE 2021), Oct, 2021.
Journal Papers
1.
S. Kawai, R. Ito, K. Nakata, Y. Shimizu, M. Nagata, T. Takeuchi, H. Kobayashi, K.
Ikeuchi, T. Kato, Y. Hagiwara, Y. Fujimura, K. Yoshioka , S. Saigusa, H. Yoshida, M. Arai,
T. Yamagishi, H. Kajihara, K. Horiuchi, H. Yamada, T. Suzuki, Y, Ando, K. Nakanishi, K.
Ban, M. Sekiya, Y. Egashira, T. Aoki, K. Onizuka, and T. Mitomo. “An 802.11ax 4×4
spectrum-efficient
WLAN
AP
transceiver
SoC
supporting
1024QAM
with
frequency-dependent IQ calibration and integrated interference analyzer” IEEE J. of
Solid-State Circuits, vol. 53, no. 12, pp. 3688-3699, Dec. 2018.
2.
S. Kawai, T. Yamagishi, Y. Hagiwara, S. Saigusa, I. Seto, S. Otaka and S. Ito. "A
1024-QAM Capable WLAN Receiver with ?56.3 dB Image Rejection Ratio Using
138
Self-Calibration Technique," IEICE Trans. on Electron., vol. E80-C, no. 4, pp. 573-581,
April 2017
Presentations at International Conference
1.
S. Kawai, H. Aoyama, R. Ito, Y. Shimizu, M. Ashida, A. Maki, T. Takeuchi, H. Kobayashi,
G. Urakawa, H. Hoshino, S. Saigusa, K. Koyama, M. Morita, R. Nihei, D. Goto, M.
Nagata, K. Nakata, K. Ikeuchi, K. Yoshioka1, R. Tachibana, M. Arai, C-K. Teh, A. Suzuki,
H. Yoshida, Y. Hagiwara, T. Kato, I. Seto, T. Horiguchi, K. Ban, K. Takahashi, H. Kajihara,
T. Yamagishi, Y. Fujimura, K. Horiuchi, K. Nonin, K. Kurose, H. Yamada, K. Taniguchi,
M. Sekiya, T. Tomizawa, D. Taki, M. Ikuta, T. Suzuki, Y. Ando, D. Yashima, T. Kaihotsu,
H. Mori, K. Nakanishi, T. Kumagaya, Y. Unekawa, T. Aoki, K. Onizuka, and T. Mitomo.
“An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM
with frequency-dependent IQ calibration and integrated interference analyzer," 2018 IEEE
International Solid - State Circuits Conference (ISSCC).
2.
S. Kawai, T. Yamagishi, Y. Hagiwara, S. Saigusa, I. Seto, S. Otaka, and S. Ito. “A
1024-QAM capable WLAN receiver with −56.3 dB image rejection ratio using
self-calibration technique” 2017 IEEE International Symposium on Circuits and Systems
(ISCAS).
3.
S. Kawai, T. Wang, T. Mitomo, and S. Saigusa. “A Temperature Variation Tolerant 60 GHz
Low Noise Amplifier with Current Compensated Bias Circuit” 2013 IEEE Asian Solid
State Circuits Conference (A-SSCC).
4.
S. Kawai, T. Mitomo, and S. Saigusa. “A 60GHz CMOS rectifier with −27.5dBm
sensitivity for mm-Wave power detection” 2012 IEEE Asian Solid State Circuits
Conference (A-SSCC).
5.
S. Kawai, H. Ishikuro, and T. Kuroda. “A 2.5Gb/s/ch 4PAM inductive-coupling transceiver
for non-contact memory card” 2010 IEEE International Solid- State Circuits Conference
(ISSCC).
6.
S. Kawai, H. Ishikuro, and T. Kuroda. “A 4.7Gb/s Inductive Coupling Interposer with
Dual Mode Modem” 2009 IEEE Symposium on VLSI Circuits.
139
7.
S. Kawai, T. Ikari, Y. Takikawa, H. Ishikuro, and T. Kuroda. “A wireless real-time on-chip
bus trace system using quasi-synchronous parallel inductive coupling transceivers” 2008
IEEE Asian Solid State Circuits Conference (A-SSCC).
Journal Papers (Co-Author)
1.
K. Niitsu, S. Kawai, N. Miura, H. Ishikuro, and T. Kuroda. “A 65fJ/b Inter-Chip
Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power
Inter-Chip Communication in 3-D System Integration” IEEE Trans. on Very Large Scale
Integ. (VLSI) Systems. vol. 20, no. 7, pp. 1285-1294, Jul. 2012.
2.
N. Miura, T. Shidei, Y. Yuan, S. Kawai, K. Takatsu, Y. Kiyota, Y. Asano and T. Kuroda. “A
0.55 V 10 fJ/bit Inductive-Coupling Data Link and 0.7 V 135 fJ/Cycle Clock Link With
Dual-Coil Transmission Scheme” IEEE J. of Solid-State Circuits, vol. 46, no. 4, pp.
965-073, Apr. 2011.
Presentations at International Conference (Co-Author)
1.
M. Sandell, X. Wang, G. Watkins, S. Kawai, T. Ueno, and K. Onizuka. “Multiobjective
optimisation of active gate drivers for fast-switching MOSFETs” IEEE Energy Conversion
Congress & Exposition (ECCE 2022), Oct, 2022.
2.
A. Shirane, S. Kawai, H. Aoyama, R. Ito, T. Mitomo, H. Kobayashi, H. Yoshida, H.
Majima, R. Fujimoto, And H. Tsurumi. “A low voltage 0.8V RF receiver in 28nm CMOS
for 5GHz WLAN” 2017 IEEE European Solid State Circuits Conference (ESSCIRC)
3.
S. Saigusa, T. Mitomo, H. Okuni, M. Hosoya, A. Sai, S. Kawai, T. Wang, M. Furuta, K.
Shiraishi, K. Ban, S. Horikawa, T. Tandai, R. Matsuo, T. Tomizawa, H. Hoshino, J.
Matsuno, Y. Tsutsumi, R. Tachibana, O. Watanabe, and T. Itakura. “A fully integrated
single-chip 60GHz CMOS transceiver with scalable power consumption for proximity
wireless communication” 2014 IEEE International Solid- State Circuits Conference (ISSCC)
4.
N. Miura, T. Shidei, Y. Yuan, S. Kawai, K. Takatsu, Y. Kiyota, Y. Asano and T. Kuroda. “A
0.7V 20fJ/bit inductive-coupling data link with dual-coil transmission scheme” 2010
140
Symposium on VLSI Circuits.
5.
K. Niitsu, S. Kawai, N. Miura, H. Ishikuro and T. Kuroda. “A 65 fJ/b inductive-coupling
inter-chip transceiver using charge recycling technique for power-aware 3D system
integration” 2008 IEEE Asian Solid State Circuits Conference (A-SSCC).
141
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