Clean Energy Conversion Research Section

概要

For the 2D/2D interfacial properties in TFET, the defect-free clean heterointerface is critical for obtaining the BTBT dominant current under reverse bias at the diode. Although the BTBT current has been demonstrated at low temperatures [1], thermally activated behavior often appears at higher temperatures near RT. That is, the generation current governs the total current, resulting in degradation of the SS at RT. This suggests that interface states exist even for 2D/2D interfaces. In general, high-Z: top gate oxides have been used in most of 2D TFETs reported thus far to enhance the gate capacitance. However, how the quality of the 2D/2D interface is affected by the deposition of high-Z: oxides has not been revealed yet. Therefore, comparisons between high-Z: and A-BN gate insulators should be carried out systematically in the same 2D TFET system because the use of A-BN in TFETs has been quite limited.

In this work, we systematically studied all 2D heterostructure TFETs produced by combining the type III H-M0S2//T-M0S2 heterostructure with the h- BN top gate in order to achieve SS values less than 60 mVdec’1 at RT.

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