Compact Superconducting Lookup Table Composed of Two-Dimensional Memory Cell Array Reconfigured by External DC Control Currents

Fig. 9. Comparison of (a) circuit area and (b) number of JJs of the new LUT

and those of the conventional LUT [12].

the low-temperature stage, the number of cables that connect the

low-temperature and room-temperature stages can be reduced.

Because once the memory cell array in the LUT is reconfigured,

the bias voltage supplied to the CMOS circuit can be turned

off and, therefore, using the CMOS circuit does not increase the

power consumption of the LUT system during its operation. The

SFQ/CMOS hybrid LUT system can be built using conventional

circuit technologies [35]–[37].

V. CONCLUSION

We investigated the compact and scalable SFQ LUT based on

the new memory cell, the datum of which is written by applying

dc control currents. The use of the new memory cell can remove

the complicated wiring in the memory cell array for reconfiguring and resetting the LUT. We designed and experimentally

confirmed the operation of the memory cells and the 4-b LUT

with wide operating margins. We found that the area of the

16-b LUT that employs the new memory cell is smaller than

that of the conventional 16-b LUT by approximately 25%. The

area reduction ratio is estimated to be larger with an increase

in the LUT bit-capacity. These results indicate the effectiveness

of introducing the memory cell proposed in this study into the

large-scale SFQ LUT.

ACKNOWLEDGMENT

The circuits were fabricated in the clean room for analogdigital superconductivity (CRAVITY) of National Institute of

Advanced Industrial Science and Technology (AIST) with the

standard process 2 (STP2) and high-speed standard process

(HSTP).

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Takuya Hosoya received the B.E. degree in electrical and computer engineering

from Yokohama National University, Yokohama, Japan, in 2019. He is currently

working toward the master’s degree in electrical engineering with the Graduate

School of Engineering Science, Yokohama National University.

Yuki Yamanashi (Member, IEEE) received the B.E., M.E., and Ph.D. degrees

in electrical and computer engineering from Yokohama National University,

Yokohama, Japan, in 2003, 2005, and 2007, respectively.

From 2007 to 2012, he was with Interdisciplinary Research Center, Yokohama

National University. Since 2012, he has been with Department of Electrical and

Computer Engineering, Yokohama National University. His research interests

include superconductive circuit design and its applications.

Dr. Yamanashi is a member of the Institute of Electronics, Information and

Communication Engineers of Japan, the Japan Society of Applied Physics, the

Institute of Electrical Engineering of Japan, Cryogenics and Superconductivity

Society of Japan, and the Institute of Electrical and Electronics Engineers.

Nobuyuki Yoshikawa (Senior Member, IEEE) received the B.E., M.E., and

Ph.D. degrees in electrical and computer engineering from Yokohama National

University, Yokohama, Japan, in 1984, 1986, and 1989, respectively.

Since 1989, he has been with the Department of Electrical and Computer

Engineering, Yokohama National University, where he is currently a Professor.

His research interests include superconductive devices and their application in

digital and analog circuits. He is also interested in single-electron-tunneling

devices, quantum computing devices and cryo-CMOS devices.

Dr. Yoshikawa is a member of the Institute of Electronics, Information and

Communication Engineers of Japan, the Japan Society of Applied Physics, the

Institute of Electrical Engineering of Japan, and the Institute of Electrical and

Electronics Engineers.

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