[1] Deloitte, “Global mobile consumer trends: Second edition”, Analysis, 2017.
[2] Isla McKetta, Ookla Insights Articles - Growing and Slowing: The State of 5G Worldwide in 2021, 2021. [Online]. Available: https://www.ookla.com/ articles/state-of-worldwide-5g-2021.
[3] Yun Chao Hu and Miran Patel and Dario Sabella and Nurit Spereher and Valerie Young, “Mobile Edge Computing A Key Technology towards 5G”, ESTI(European Telecommunication Standards Institute), White Paper, 2015.
[4] u. s. O-RAN ALLIANCE e.V.
[5] Y. Mao, C. You, J. Zhang, K. Huang, and K. B. Letaief, “A Survey on Mobile Edge Computing: The Communication Perspective”, IEEE Communications Surveys & Tutorials, vol. 19, no. 4, pp. 2322–2358, 2017. DOI: 10 . 1109 / COMST.2017.2745201.
[6] N. Abbas, Y. Zhang, A. Taherkordi, and T. Skeie, “Mobile Edge Computing: A Survey”, IEEE Internet of Things Journal, vol. 5, no. 1, pp. 450–465, 2018. DOI: 10.1109/JIOT.2017.2750180.
[7] J. Shashirangana, H. Padmasiri, D. Meedeniya, and C. Perera, “Automated license plate recognition: A survey on methods and techniques”, IEEE Access, vol. 9, pp. 11 203–11 225, Dec. 2020. DOI: 10.1109/ACCESS.2020.3047929.
[8] NEC Corporation, Press Release - NEC provides face recognition demo system utilizing MEC to DOCOMO 5G Open Lab OKINAWA, Jan. 2019. [Online]. Available: https://www.nec.com/en/press/201901/global_20190116_02.html.
[9] X. Li, Y. Tian, F. Zhang, S. Quan, and Y. Xu, “Object detection in the context of mobile augmented reality”, CoRR, vol. abs/2008.06655, 2020. arXiv: 2008. 06655. [Online]. Available: https://arxiv.org/abs/2008.06655.
[10] Advantech, Advantech 5G Edge Servers for vRAN & MEC | Private 5G Networks for IIoT | 5G Edge Computing. [Online]. Available: https://www2. advantech.com/nc/spotlight/5G/.
[11] J. Fowers, G. Brown, P. Cooke, and G. Stitt, “A Performance and Energy Comparison of FPGAs, GPUs, and Multicores for Sliding-Window Applications”, in Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, ser. FPGA ’12, Monterey, California, USA: Association for Computing Machinery, 2012, 47âĂ Ş56, ISBN: 9781450311557. DOI: 10.1145/2145694.2145704. [Online]. Available: https://doi.org/10.1145/2145694.2145704.
[12] S. Biookaghazadeh, M. Zhao, and F. Ren, “Are FPGAs Suitable for Edge Computing?”, in USENIX Workshop on Hot Topics in Edge Computing (HotEdge 18), Boston, MA: USENIX Association, Jul. 2018. [Online]. Available: https://www. usenix.org/conference/hotedge18 / presentation / biookaghazadeh.
[13] K. Musha, T. Kudoh, and H. Amano, “Deep learning on high performance FPGA switching boards: Flow-in-cloud”, English, in Applied Reconfigurable Computing, ser. Lecture Notes in Computer Science, Germany: Springer Verlag, Jan. 2018, pp. 43–54, ISBN: 9783319788890. DOI: 10.1007/978-3- 319-78890-6_4.
[14] P. Ranaweera, A. Jurcut, and M. Liyanage, “MEC Enabled 5G Use Cases: A Survey on Security Vulnerabilities and Countermeasures”, ACM Computing Surveys, Jul. 2021.
[15] Fujitsu Limited, Press releases | Fujitsu Launches Japan’s First Commercial Private 5G Network, 2020. [Online]. Available: https://www.fujitsu.com/global/about/resources/news/press-releases/2020/0327-01.html.
[16] “The Business Case for MEC in Retail: A TCO Analysis and its Implications in the 5G Era”, iGillottResearch, Inc., White Paper, 2017.
[17] Ken Sherriff, Reverse-engineering the first FPGA chip, the XC2064. [Online]. Available: http://www.righto.com/2020/09/reverse-engineering-first-fpga- chip.html.
[18] John McMaster, xc2064-70. [Online]. Available: https : / / siliconpr0n . org / archive/doku.php?id=mcmaster:xilinx:xc2064-70.
[19] Intel Corporation, Intel Arria 10 FPGAs & SoCs. [Online]. Available: https://www.intel.com/content/www/us/en/products/details/fpga/arria/10.html.
[20] Xilinx, Inc., UltraRAM: Breakthrough Embedded Memory Integration on UltraScale+ Devices. [Online]. Available: https://docs.xilinx.com/v/u/en- US/wp477-ultraram.
[21] Xilinx, Inc, Zynq-7000 SoC, 2018. [Online]. Available: https://www.xilinx. com/products/silicon-devices/soc/zynq-7000.html.
[22] Wikichip.org, Xeon Gold 6138P - Intel. [Online]. Available: https : / / en . wikichip.org/wiki/intel/xeon_gold/6138p.
[23] Xilinx Inc., MicroBlaze Soft Processor Core. [Online]. Available: https://www. xilinx.com/products/design-tools/microblaze.html.
[24] OpenRISC Community. [Online]. Available: https://openrisc.io/.
[25] N. Eskandari, N. Tarafdar, D. Ly-Ma, and P. Chow, “A Modular Heterogeneous Stack for Deploying FPGAs and CPUs in the Data Center”, in Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ser. FPGA ’19, Seaside, CA, USA: Association for Computing Machinery, 2019, 262âĂ Ş271, ISBN: 9781450361378. DOI: 10.1145/3289602.3293909. [Online]. Available: https://doi.org/10.1145/3289602.3293909.
[26] B. Ringlein, F. Abel, A. Ditter, B. Weiss, C. Hagleitner, and D. Fey, “Programming Reconfigurable Heterogeneous Computing Clusters Using MPI With Transpiration”, in 2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC), 2020, pp. 1–9. DOI: 10.1109/H2RC51942.2020.00006.
[27] A. Putnam, A. M. Caulfield, E. S. Chung, D. Chiou, K. Constantinides, J. Demme, H. Esmaeilzadeh, J. Fowers, G. P. Gopal, J. Gray, M. Haselman, S. Hauck, S. Heil, A. Hormati, J.-Y. Kim, S. Lanka, J. Larus, E. Peterson, S. Pope, A. Smith, J. Thong, P. Y. Xiao, and D. Burger, “A Reconfigurable Fabric for Accelerating Large-scale Datacenter Services”, in Proceeding of the 41st Annual International Symposium on Computer Architecture, ser. ISCA ’14, Minneapolis, Minnesota, USA: IEEE Press, 2014, pp. 13–24, ISBN: 978-1-4799-4394-4.
[28] Intel Corporation, Serial Lite III Streaming IntelÂő FPGA IP User Guide. [Online]. Available: https://www.intel.com/content/www/us/en/docs/programmable/683330/21-3-19-3-0/quick-reference.html.
[29] A. M. Caulfield, E. S. Chung, A. Putnam, H. Angepat, J. Fowers, M. Haselman, S. Heil, M. Humphrey, P. Kaur, J.-Y. Kim, D. Lo, T. Massengill, K. Ovtcharov, M. Papamichael, L. Woods, S. Lanka, D. Chiou, and D. Burger, “A cloud-scale acceleration architecture”, in 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2016, pp. 1–13. DOI: 10.1109/MICRO.2016.7783710.
[30] J. Fowers, K. Ovtcharov, M. Papamichael, T. Massengill, M. Liu, D. Lo, S. Alkalay, M. Haselman, L. Adams, M. Ghandi, S. Heil, P. Patel, A. Sapek, G. Weisz, L. Woods, S. Lanka, S. K. Reinhardt, A. M. Caulfield, E. S. Chung, and D. Burger, “A Configurable Cloud-Scale DNN Processor for Real-Time AI”, in 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA), 2018, pp. 1–14. DOI: 10.1109/ISCA.2018.00012.
[31] N. Tarafdar, N. Eskandari, V. Sharma, C. Lo, and P. Chow, “Galapagos: A Full Stack Approach to FPGA Integration in the Cloud”, IEEE Micro, vol. 38, no. 6, pp. 18–24, 2018. DOI: 10.1109/MM.2018.2877290.
[32] S. Byma, J. G. Steffan, H. Bannazadeh, A. L. Garcia, and P. Chow, “FPGAs in the Cloud: Booting Virtualized Hardware Accelerators with OpenStack”, in 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines, 2014, pp. 109–116. DOI: 10.1109/FCCM.2014. 42.
[33] Amazon Web Services, Inc., Amazon EC2 F1 Instance, https://aws.amazon. com/jp/ec2/instance-types/f1/.
[34] Jeff Barr, AWS News Blog - Developer Preview - EC2 Instances (F1) with Programmable Hardware, https://aws.amazon.com/jp/blogs/aws/developer- preview-ec2-instances-f1-with-programmable-hardware/, 30.
[35] F. Abel, J. Weerasinghe, C. Hagleitner, B. Weiss, and S. Paredes, “An FPGA Platform for Hyperscalers”, in 2017 IEEE 25th Annual Symposium on High-Performance Interconnects (HOTI), 2017, pp. 29–32. DOI: 10.1109/ HOTI.2017.13.
[36] P. Moorthy and N. Kapre, “Zedwulf: Power-Performance Tradeoffs of a 32-Node Zynq SoC Cluster”, in 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, 2015, pp. 68–75.
[37] Samtec, Inc., Micro Flyover On-Board Optical Engine, FireFly. [Online]. Available: https://www.samtec.com/optics/optical-cable/mid-board/firefly.
[38] K. Hironaka, N. A. V. Doan, and H. Amano, “Towards an Optimized Multi FPGA Architecture with STDM Network: A Preliminary Study”, in Applied Reconfigurable Computing. Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings, 2018, pp. 142–150. DOI: 10.1007/978-3-319-78890-6\_12. [Online]. Available: https://doi.org/10.1007/978-3-319-78890-6\_12.
[39] Xilinx, Inc., Vivado High Level Synthesis. [Online]. Available: https://www. xilinx.com/video/hardware/vivado-high-level-synthesis.html.
[40] ——, Aurora 64B/66B. [Online]. Available: https://www.xilinx.com/products/ intellectual-property/aurora64b66b.html.
[41] ——, Memory Interface. [Online]. Available: https : / / www . xilinx . com / products/intellectual-property/mig.html.
[42] PALTEK, FPGA computing platform M-KUBOS. [Online]. Available: https://www.paltek.co.jp/design/original/m-kubos/.
[43] K. Tomohiro, T. Ryosei, A. Hideharu, K. Michihiro, M. Hiroki, H. Toshihiro, I. Tsutomu, S. Kuniyasu, T. Akira, A. Erio, N. Shu, and K. Taura, “Flow in Cloud: A dataflow centric cloud system of heterogeneous engines”, TECHNICAL REPORT OF IEICE vol. 117 no. 153 CPSY2017-16, pp. 1–5, 2017.
[44] Xilinx, Inc, PYNQ | Python productivity for Zynq, 2019. [Online]. Available: http://www.pynq.io/.
[45] J. Sheng, C. Yang, T. Wang, and M. C. Herbordt, “High Performance Dynamic Communication on Reconfigurable Clusters”, in 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018, Boulder, CO, USA, April 29 - May 1, 2018, 2018, p. 219. DOI: 10.1109/FCCM.2018.00053. [Online]. Available: https://doi.org/ 10.1109/FCCM.2018.00053.
[46] Y. Hu, T. Kudoh, and M. Koibuchi, “A Case of Electrical Circuit Switched Interconnection Network for Parallel Computers”, in 2017 18th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT), 2017, pp. 276–283. DOI: 10 . 1109 / PDCAT . 2017 . 00052.
[47] R. Stefan and K. Goossens, “Multi-path routing in time-division-multiplexed networks on chip”, in 2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC), 2009, pp. 109–114. DOI: 10.1109/VLSISOC. 2009.6041339.
[48] M. Schoeberl, F. Brandner, J. Sparsø, and E. Kasapaki, “A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems”, in 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), Copenhagen, Denmark, 9-11 May, 2012, 2012, pp. 152–160. DOI: 10.1109/NOCS.2012.25. [Online]. Available: https://doi.org/10.1109/NOCS. 2012.25.
[49] K. Ito, K. Iizuka, K. Hironaka, Y. Hu, K. Koibuchi, and H. Amano, “Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System”, in 2020 Eighth International Symposium on Computing and Networking Workshops (CANDARW), 2020, pp. 211–217.
[50] K. Azegami, K. Musha, K. Hironaka, A. B. Ahmed, M. Koibuch, Y. Hu, and H. Amano, “A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System”, in 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 2019, pp. 328–333. DOI: 10.1109/MCSoC.2019.00053.
[51] Khronos Group Inc., OpenCL | Open Standard for Parallel Programming of Heterogeneous Systems. [Online]. Available: https://www.khronos.org/opencl/.
[52] Xilinx, Inc., SDAccel Development Environment. [Online]. Available: https://www.xilinx.com/products/design-tools/legacy-tools/sdaccel.html.
[53] Intel Corporation, Intel FPGA SDK for OpenCL Software Technology. [Online]. Available: https://www.intel.com/content/www/us/en/software/ programmable/sdk-for-opencl/overview.html.
[54] Y. SUN and H. AMANO, “FiC-RNN: A Multi-FPGA Acceleration Framework for Deep Recurrent Neural Networks”, IEICE Transactions on Information and Systems, vol. E103.D, no. 12, pp. 2457–2462, 2020. DOI: 10.1587/transinf.2020PAP0003.
[55] Y. Yamauchi, A. B. Ahmed, K. Hironaka, K. Iizuka, and H. Amano, “Horizontal division of deep learning applications with all-to-all l communication on a multi-FPGA system”, in 2020 Eighth International Symposium on Computing and Networking Workshops (CANDARW), 2020, pp. 277–281. DOI: 10.1109/CANDARW51189.2020.00060.
[56] Y. Fukushima, K. Iizuka, and H. Amano, “Parallel Implementation of CNN on Multi-FPGA Cluster”, English, in 2021 IEEE 14th International Symposium on Embeded Multicore/Manu-core Systems-on-Chip (MCSoC), Dec. 2021.
[57] R. T. Fielding, “Architectural styles and the design of network-based software architectures”, Publication, University of California, Irvine, 2000. [Online]. Available: https://www.ics.uci.edu/~fielding/pubs/dissertation/top.htm.
[58] Xilinx, Inc., Integrated Logic Analyzer (ILA). [Online]. Available: https : / / www.xilinx.com/products/intellectual-property/ila.html.
[59] ——, Xilinx Virtual Cable. [Online]. Available: https://github.com/Xilinx/ XilinxVirtualCable.
[60] ESTI, ESTI GS MEC 003 v3.1.1 (2022-03) - Multi-access Edge Computing (MEC) Framework and Reference Architecture. 2022.
[61] M. YAMAKURA, R. Takano, A. AHMED, M. Sugaya, and H. AMANO, “A Multi-Tenant Resource Management System for Multi-FPGA Systems”, IEICE Transactions on Information and Systems, vol. E104.D, pp. 2078–2088, Dec. 2021. DOI: 10.1587/transinf.2021PAP0005.
[62] Slurm Workload Manager. [Online]. Available: https://slurm.schedmd.com/.
[63] IBM Spectrum LSF Suites. [Online]. Available: https://https://www.ibm.com/ products/hpc-workload-management/.
[64] M. Yamakura, K. Hironaka, K. Azegami, K. Musha, and H. Amano, “The Evaluation of Partial Reconfiguration for a Multi-Board FPGA System FiCSW”, in Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, ser. HEART 2019, Nagasaki, Japan: Association for Computing Machinery, 2019, ISBN: 9781450372558. DOI: 10.1145/3337801.3337805. [Online]. Available: https://doi.org/10.1145/3337801.3337805.
[65] Armin Ronacher, Flask (A Python microframework). [Online]. Available: http://flask.pocoo.org/.
[66] Future Technology Devices International Ltd., FT232H - Hi-Speed Single Channel USB UART/FIFO IC. [Online]. Available: https://www. ftdichip . com/old2020/Products/ICs/FT232H.htm.
[67] Felix Domke (tmbinc), xvcd - Xilinx Virtual Cable Daemon. [Online]. Available: ttps://github.com/tmbinc/xvcd.
[68] B. Ringlein, F. Abel, A. Ditter, B. Weiss, C. Hagleitner, and D. Fey, “System Architecture for Network-Attached FPGAs in the Cloud using Partial Reconfiguration”, in 2019 29th International Conference on Field Programmable Logic and Applications (FPL), 2019, pp. 293–300. DOI: 10. 1109/FPL.2019.00054.
[69] B. Ringlein, F. Abel, D. Diamantopoulos, B. Weiss, C. Hagleitner, M. Reichenbach, and D. Fey, “A Case for Function-as-a-Service with Disaggregated FPGAs”, in 2021 IEEE 14th International Conference on Cloud Computing (CLOUD), 2021, pp. 333–344. DOI: 10 . 1109 / CLOUD53861.2021.00047.
[70] P. Bomel, J. Crenne, L. Ye, J.-P. Diguet, and G. Gogniat, “Ultra-Fast Downloading of Partial Bitstreams through Ethernet”, in Architecture of Computing Systems – ARCS 2009, M. Berekovic, C. Müller-Schloer, C. Hochberger, and S. Wong, Eds., Berlin, Heidelberg: Springer Berlin Heidelberg, 2009, pp. 72–83, ISBN: 978-3-642-00454-4.
[71] J. Vidal, F. de Lamotte, G. Gogniat, J.-P. Diguet, and P. Soulard, “UML Design for Dynamically Reconfigurable Multiprocessor Embedded Systems”, in Proceedings of the Conference on Design, Automation and Test in Europe, ser. DATE ’10, Dresden, Germany: European Design and Automation Association, 2010, 1195âĂ Ş1200, ISBN: 9783981080162.
[72] Muhammed Al Kadi and Patrick Rudolph and Diana Göhringer and Michael Hübner, “Dynamic and partial reconfiguration of Zynq 7000 under Linux”, 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig), pp. 1–5, 2013.
[73] D. Wanta, W. T. Smolik, J. Kryszyn, P. Wróblewski, and M. Midura, “A Run-Time Reconfiguration Method for an FPGA-Based Electrical Capacitance Tomography System”, Electronics, vol. 11, no. 4, 2022, ISSN: 2079-9292. DOI: 10 . 3390 / electronics11040545. [Online]. Available: https ://www.mdpi.com/2079-9292/11/4/545.
[74] J. L. Elman, “Finding Structure in Time”, Cognitive Science, vol. 14, no. 2, pp. 179–211, 1990. DOI: https://doi.org/10.1207/s15516709cog1402 \ _1. eprint: https://onlinelibrary.wiley.com/doi/pdf/10.1207/s15516709cog1402_1. [Online]. Available: https://onlinelibrary. wiley.com/doi/abs/10.1207/s15516709cog1402_1.
[75] Y. LeCun, B. Boser, J. S. Denker, D. Henderson, R. E. Howard, W. Hubbard, and L. D. Jackel, “Backpropagation Applied to Handwritten Zip Code Recognition”, Neural Computation, vol. 1, no. 4, pp. 541–551, 1989. DOI: 10.1162/neco.1989.1.4.541.
[76] K. He, X. Zhang, S. Ren, and J. Sun, “Deep Residual Learning for Image Recognition”, in 2016 IEEE Conference on Computer Vision and Pattern Recognition (CVPR), 2016, pp. 770–778. DOI: 10.1109/CVPR.2016.90.
[77] R. Polig, J. Weerasinghe, and C. Hagleitner, “RESTful Web Services on Standalone Disaggregated FPGAs”, Jan. 2021. DOI: 10 . 36227 / techrxiv . 13560317.v1. [Online]. Available: https://www.techrxiv.org/articles/preprint/RESTful_Web_Services_on_Standalone_Disaggregated_FPGAs/13560317.
[78] H. Seo, C. Sadowski, S. Elbaum, E. Aftandilian, and R. Bowdidge, “Programmers’ Build Errors: A Case Study (at Google)”, in Proceedings of the 36th International Conference on Software Engineering, ser. ICSE 2014, Hyderabad, India: Association for Computing Machinery, 2014, 724âĂ Ş734, ISBN: 9781450327565. DOI: 10.1145/2568225.2568255. [Online]. Available: https://doi.org/10.1145/2568225.2568255.
[79] Himeno benchmark. [Online]. Available: https : / / i . riken . jp / en / supercom / documents/himenobmt/.
[80] Brown, Nick and Dolman, David, “It’s All About Data Movement: Optimising FPGA Data Access to Boost Performance”, in 2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC), 2019, pp. 1–10. DOI: 10.1109/H2RC49586.2019.00006.
[81] M. Saldana and P. Chow, “TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs”, in 2006 International Conference on Field Programmable Logic and Applications, 2006, pp. 1–6. DOI: 10.1109/ FPL.2006.311233.
[82] Open MPI: Open Source High Performance Computing. [Online]. Available: https://www.open-mpi.org/.
[83] MPICH | High-Performance Portable MPI. [Online]. Available: https://www. mpich.org/.