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Shallow defect layer formation as Cu gettering layer of ultra-thin Si chips using moderate-pressure (3.3 kPa) hydrogen plasma

Nomura, Toshimitsu 大阪大学

2023.04.28

概要

The fabrication of ultra-thin Si wafers (∼5 μm) is a key
technique in three-dimensional integrated circuits (3D ICs). 3D ICs
are fabricated by three-dimensionally stacking the Si wafers and
interconnecting each stack using a through-silicon via (TSV).1–3 In
3D ICs, stacking thinner Si wafers contributes to a higher integration
of the device and a shorter TSV, which results in lower power consumption and a higher clock rate. However, as the Si wafer thickness
decreases, it tends to break due to its lower mechanical strength. In
addition, the diffusion of metal impurities from the back surface of
the wafer to the device layer is a critical issue for device reliability.
Metal contamination should be avoided because it can result in the
degradation of transistor performance.4 By using a thick
Czochralski-grown Si (Cz-Si) wafer, oxide precipitates in the Si bulk
(due to an oxygen solid solution of 1017–1018 cm–3) can trap metal
impurities to protect the device layer from metal contamination,5–8
also known as intrinsic gettering (IG). However, when the wafer is
thinned down to less than 10 μm,9 IG is no longer effective in protecting a device layer. ...

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